In this exampel we blink a LED each second. My FPGA, Cyclone IV board has a 50MHz clock so we need to count up to 50 million and then invert the LED status. Below, you have the entire project ready to downlaod. Open it in Quartus and create the synthesis for your FPGA.
module blink (clk, LED);
input clk;
output LED;
reg [31:0] counter;
reg LED_status;
initial begin
counter <= 32'b0;
LED_status <= 1'b0;
end
always @ (posedge clk)
begin
counter <= counter + 1'b1;
if (counter > 50000000)
begin
LED_status <= !LED_status;
counter <= 32'b0;
end
end
assign LED = LED_status;
endmodule
