Logic gates

logic gates - baic tutorial

Part 8 - SR latch

Ok, let’s see how the SR is made and what this flip flop dose. Using the logic gates before, we can create a SR latch very easy. All we need are two NOR gates. The first nor output is called Q and the second negative Q. The top input is Reset and the bottom set. This is the truth table of the NOR gate as seen before. Before we power up this circuit everything is low and painted with blue. I will paint high signals with red so it will be easier to understand.

SR latch tutorial

If all the inputs are low, according to the truth table the output of 0 0 will be a one. But this one is connected at the input of the second NOR gate so its output will be still 0.

So, without changing the inputs Q will be high and it will stay high till next input change and that’s important since that’s the job of a latch. The bottom NOR gate has the inputs at 1 and a 0 so the output is still 0. Now let’s apply a high pulse at the Reset pin. The input is now a 1 and 0 and the output will drop at 0 according to the truth table. But the output of the first is the input of the second so now the second has two low inputs so the output negative Q will be high. Now if I activate the Set pin we will have a one and a 0 so the output will drop once again to 0 and since. If we don’t care about the inverted Q output, this system output is very easy. Press the Set and turn it high and it will stay high till you press the reset and turn it low.

PART 9 - Inside logic gates

Inside, each logic gate is made out of transistors. As an example here, we have the schematics for AND and OR gates with two inputs made with NPN transistors. Consider the transistors as a normal switch activated with a one and deactivated with a o. In case of this double input and, we have 5 volts, then our output, then the two transistors in series and then ground. If I activate just one of these switches the current flow won’t be possible. Only when I activate both of them and that makes this circuit a AND gate. In case of the OR hate the transistors ate placed in parallel so any of the transistors could close the circuit. If I activate the A transistors current flows thru this path and if I activate B thru the right path and if both are activated the output is still high and that’s how an OR gate works.

logic gate tutorial

Part 10 - MUX

Ok guys, before we end this basic intro to the logic world, I want to talk about multiplexors which will appear in any RTL diagram of any simple circuit. This is the symbol of a multiplexor also called a MUX. They usually have a 2 to the n amount of inputs se we have 2, 4, 8, 16 and so on. On one side we have the inputs, on the other the output and on the bottom are the selector pins.

Let’s say we have a 8 input MUX. We apply the binary input at the selector pins and allow one of the 8 inputs at the output where a 001 is the first input, 010 the second 011 the third and so on as in this table. So that easy with 3 signals we can select any of the 8 inputs. This module is also very commune in logic circuits.

NOT gate tutorial

Well guys, now we know the basics, but very, very, basics of the logic word. Next, we will see how to work with logic functions as Boolean algebra, how to simplify the functions using the Karnaugh tables and then we pass to Verilog which is not a programming language but a logic circuit describing one.

Once we know Verilog, we can start programming our FPGA and see some examples in the Quartus software. Stay tuned for future parts of this logic series of videos. Check the links below for my webpage for more details and photos, more schematics of the internal structures of logic gates, sticks diagram, RTL viewer and so on. Also, if you would like to support this kind of tutorials, check my Patreon page. I really need your help and continue with this kind of videos. I would appreciate that guys.

See Karnaugh table: Or go back:

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